Development Board - Company Ranking(13 companyies in total)
Last Updated: Aggregation Period:Jul 23, 2025〜Aug 19, 2025
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![]() T-Core
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■Specifications FPGA Device - MAX 10 10M50DAF484C7G Device - Integrated Dual ADC - 50K Programmable Logic Elements - 1,638 Kbit M9K Memory - 5,888 Kbit User Flash Memory - 144 18×18 Multipliers - Four PLLs User Interface - Buttons x2 - Dip Switches x4 - Green LEDs x4 - RGB LEDs x4 JTAG - USB-Blaster II for MAX 10 - USB-Blaster II for RISC-V - JTAG Master for other boards Clock and Memory Devices - Two 50 MHz Single-Ended External Oscillator Clock Sources - One 10 MHz Single-Ended External Oscillator Clock Source - 64Mb QSPI Flash (for storing RISC-V code) Expansion Connectors - 2x6 TMD Expansion Header - 1x10 ADC Header - Two 1x3 RGB LED Expansion Headers Power - USB Type Mini-AB Port (5V) - 2-Pin External Power Header (4.4-5.6V) | Development of RISC-V cores Learning FPGA development Product development using RISC-V cores | |
【Specifications (Excerpt)】 ■FPGA Device ・MAX10 (10M50DAF484C7G) ■FPGA Configuration ・Onboard USB Blaster (Normal USB B connector) ■Memory Device ・64MB SDRAM (x16 data bus) ■Sensor ・Accelerometer ■Expansion Connector ・2x20 GPIO Connector (3.3V) ・Arduino Uno R3 Connector (including 6 ADC channels) *For more details, please refer to the external link page or feel free to contact us. | For more details, please refer to the external link page or feel free to contact us. | ||
【Specifications (Excerpt)】 ■FPGA Device ・Cyclone V 5CEBA4F23C7N Device ・49K Programmable Logic Elements ・3080 Kilobits Embedded Memory ・4 Fractional PLLs ・1 Hard Memory Controller ■Configuration and Debugging ・Serial Configuration Device – EPCS64 on FPGA ・Onboard USB Blaster (Standard Type B USB Connector) ・Supports JTAG and AS Mode Configuration ■Memory Device ・64MB SDRAM, x16 Bit Data Bus ■Communication ・PS/2 Mouse/Keyboard ■Connectors ・Two 2x20 GPIO Headers *For more details, please refer to the external link page or feel free to contact us. | For more details, please refer to the external link page or feel free to contact us. | ||
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- Featured Products
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T-Core
- overview
- ■Specifications FPGA Device - MAX 10 10M50DAF484C7G Device - Integrated Dual ADC - 50K Programmable Logic Elements - 1,638 Kbit M9K Memory - 5,888 Kbit User Flash Memory - 144 18×18 Multipliers - Four PLLs User Interface - Buttons x2 - Dip Switches x4 - Green LEDs x4 - RGB LEDs x4 JTAG - USB-Blaster II for MAX 10 - USB-Blaster II for RISC-V - JTAG Master for other boards Clock and Memory Devices - Two 50 MHz Single-Ended External Oscillator Clock Sources - One 10 MHz Single-Ended External Oscillator Clock Source - 64Mb QSPI Flash (for storing RISC-V code) Expansion Connectors - 2x6 TMD Expansion Header - 1x10 ADC Header - Two 1x3 RGB LED Expansion Headers Power - USB Type Mini-AB Port (5V) - 2-Pin External Power Header (4.4-5.6V)
- Application/Performance example
- Development of RISC-V cores Learning FPGA development Product development using RISC-V cores
Development board "DE10-Lite"
- overview
- 【Specifications (Excerpt)】 ■FPGA Device ・MAX10 (10M50DAF484C7G) ■FPGA Configuration ・Onboard USB Blaster (Normal USB B connector) ■Memory Device ・64MB SDRAM (x16 data bus) ■Sensor ・Accelerometer ■Expansion Connector ・2x20 GPIO Connector (3.3V) ・Arduino Uno R3 Connector (including 6 ADC channels) *For more details, please refer to the external link page or feel free to contact us.
- Application/Performance example
- For more details, please refer to the external link page or feel free to contact us.
Development board "DE0-CV [Academic Edition]"
- overview
- 【Specifications (Excerpt)】 ■FPGA Device ・Cyclone V 5CEBA4F23C7N Device ・49K Programmable Logic Elements ・3080 Kilobits Embedded Memory ・4 Fractional PLLs ・1 Hard Memory Controller ■Configuration and Debugging ・Serial Configuration Device – EPCS64 on FPGA ・Onboard USB Blaster (Standard Type B USB Connector) ・Supports JTAG and AS Mode Configuration ■Memory Device ・64MB SDRAM, x16 Bit Data Bus ■Communication ・PS/2 Mouse/Keyboard ■Connectors ・Two 2x20 GPIO Headers *For more details, please refer to the external link page or feel free to contact us.
- Application/Performance example
- For more details, please refer to the external link page or feel free to contact us.
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